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APPLICATION NOTES AND DEVELOPMENT SYSTEM
AVAILABLE
X84041 4K
AN10 * AN17 * AN57 * XK84
X84041
Micro Port Saver E2PROM
MPSTM E2PROM
FEATURES * Direct Interface to Micros --Eliminates I/O port requirements --No interface glue logic required --Eliminates need for parallel to serial converters * 3.3Mbps data transfer rate * Low Power CMOS --2.7V to 5.5V Operation --Standby Current Less than 50A --Active Current Less than 1mA * 45ns Read Access Time * 8-Byte Page Write Mode * Typical Nonvolatile Write Cycle Time: 5ms * High Reliability --100,000 Endurance Cycles --Guaranteed Data Retention: 100 Years * 8-Lead PDIP, 8-Lead SOIC, and 14-Lead TSSOP Packages
DESCRIPTION The X84041 Micro Port Saver is a 4096-bit CMOS E2PROM designed for a direct interface to port limited microcontroller or I/O limited microprocessor designs. The X84041 provides all of the benefits of serial memories, such as low cost, low power, low voltage operation, and small package size, while featuring higher data transfer rates and reduced interface code requirements-- without the need for a dedicated serial bus. The X84041 is organized as a 512 x 8, but is also suitable in 16-bit or 32-bit environments, due to the bit serial nature of the interface. The X84041 directly connects to the processor bus and communicates over a single data line using a sequence of standard bus read and write operations. This eliminates the need for dedicated port pins, parallel to serial converters, complicated ASIC implementations, or other glue logic, lowering system cost. BLOCK DIAGRAM
WP
8 7 X84041 6 5 VCC NC OE WE
2704 ILL F01.2
PIN CONFIGURATION
DIP/SOIC CE I/O WP VSS 1 2 3 4
H.V. GENERATION TIMING & CONTROL
CE OE WE I/O COMMAND DECODE AND CONTROL LOGIC X DEC EEPROM ARRAY 512 x 8
TSSOP CE I/O NC NC NC WP VSS 1 2 3 5 6 7 14 13 12 10 9 8 VCC NC NC NC NC OE WE
2704 ILL F02a.1
Y DECODE DATA REGISTER
2704 ILL F02
4 X84041 11
PIN NAMES I/O CE OE WE WP VCC VSS NC Data Input/Output Chip Enable Input Output Enable Input Write Enable Input Write Protect Input Supply Voltage Ground No Connect
2704 PGM T01
(c) Xicor, Inc. 1994, 1995, 1996 Patents Pending 2704-4.4 6/12/96 T3/C1/D0 NS
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Characteristics subject to change without notice
X84041
A Write Protect (WP) pin provides hardware protection against inadvertent writes to the memory. Xicor E2PROMs are designed and tested for applications requiring extended endurance. Inherent data retention is greater than 100 years. PIN DESCRIPTIONS Chip Enable (CE) The Chip Enable input must be LOW to enable all read/ write operations. When CE is HIGH, the chip is deselected, the I/O pin is in the high impedance state, and unless a nonvolatile write operation is underway, the X84041 is in the standby power mode. Output Enable (OE) The Output Enable input must be LOW to enable the output buffer and to read data from the X84041 on the I/O line. Write Enable (WE) The Write Enable input must be LOW to write either data or command sequences to the X84041. Data In/Data Out (I/O) Data and command sequences are serially written to or serially read from the X84041 through the I/O pin. Write Protect (WP) When the Write Protect input is LOW, nonvolatile writes to the X84041 are disabled. When WP is HIGH, all functions, including nonvolatile writes, operate normally. If a nonvolatile write cycle is in progress, WP going LOW will have no effect on the cycle already underway, but will inhibit any additional nonvolatile write cycles. DEVICE OPERATION The X84041 is a serial 512 x 8 bit E2PROM designed to interface directly with most microprocessor buses. Standard CE, OE, and WE signals control the read and write operations, and a single l/O line is used to send and receive data and commands serially. Data Timing Data input on the l/O line is latched on the rising edge of either WE or CE, whichever occurs first. Data output on the l/O line is active whenever both OE and CE are LOW. Care should be taken to ensure that WE and OE are never both LOW while CE is LOW. Read Sequence A read sequence consists of sending a 16-bit address followed by the reading of data serially. The address is written by issuing 16 separate write cycles (WE and CE LOW, OE HIGH) to the part without a read cycle between the write cycles. The address is sent serially, most significant bit first, over the I/O line. Note that this sequence is fully static, with no special timing restrictions, and the processor is free to perform other tasks on the bus whenever the X84041 CE pin is HIGH. Once the 16 address bits are sent, a byte of data can be read on the I/O line by issuing 8 separate read cycles (OE and CE LOW, WE HIGH). At this point, issuing a reset sequence will terminate the read sequence, otherwise the X84041 will await further reads in the sequential read mode. Sequential Read The byte address is automatically incremented to the next higher address after each byte of data is read. The data stored in the memory at the next address can be read sequentially by continuing to issue read cycles. When the highest address is reached ($1FF), the address counter rolls over to address $000 and reading may be continued indefinitely. Reset Sequence The reset sequence resets the X84041 and sets an internal write enable latch. A reset sequence can be sent at any time by performing a read/write "0"/read sequence (see Figs. 1 and 2). This sequence breaks the multiple read or write cycle sequences that are normally used when reading from or writing to the part. This sequence can be used at any time to interrupt or end a sequential read or page load. As soon as the write "0" cycle is complete, the part is reset (unless a nonvolatile write cycle is in progress). The second read cycle in this sequence, and any further read cycles, will read a HIGH on the l/O pin until a valid read sequence is issued. The reset sequence must be issued at the beginning of both read and write sequences to be sure the X84041 initiates these operations properly.
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X84041
Figure 1. Read Sequence
CE
OE
WE
I/O (IN)
"0"
X
XXXXX
X A8
A7 A6 A5 A4 A3 A2 A1 A0
I/O (OUT) RESET LOAD ADDRESS
D7 D6 D5 D4 D3 D2 D1 D0
READ DATA
2704 ILL F03
Write Sequence A nonvolatile write sequence consists of sending a reset sequence, a 16-bit address (the first 7 of which are don't cares), up to 8 bytes of data, and then a special "start nonvolatile write cycle" command sequence. The reset sequence is issued first (as described in the Reset Sequence section) to set the internal write enable latch. The address is written serially by issuing 16 separate write cycles (WE and CE LOW, OE HIGH) to the part without any read cycles between the writes. The address is sent serially, most significant bit first, on the l/O pin. Up to eight bytes of data are written by issuing either 8, 16, 24, 32, 40, 48, 56, or 64 separate write cycles. Again, no read cycles are allowed between writes. The nonvolatile write cycle is initiated by issuing a special read/write "1"/read sequence. The first read cycle ends the page load, then the write "1" followed by a read starts the nonvolatile write cycle. The X84041 recognizes 8byte pages beginning at addresses XXXXXX000. When sending data to the part, attempts to exceed the upper address of the page will result in the address counter "wrapping-around" to the first address on the page,
where data loading can continue. For this reason, sending more than 64 consecutive data bits will result in overwriting previous data. A nonvolatile write cycle will not start if a partial or incomplete write sequence is issued. The internal write enable latch is reset when the nonvolatile write cycle is completed to prevent inadvertent writes. Note that this sequence is fully static, with no special timing restrictions. The processor is free to perform other tasks on the bus whenever the chip enable pin (CE) is HIGH. Nonvolatile Write Status The status of a nonvolatile write cycle can be determined at any time by simply reading the state of the l/O pin on the X84041. This pin is read when OE and CE are LOW and WE is HIGH. During a nonvolatile write cycle the l/ O pin is LOW. When the nonvolatile write cycle is complete, the l/O pin goes HIGH. A reset sequence can also be issued during a nonvolatile write cycle with the same result: I/O is LOW as long as a nonvolatile write cycle is in progress, and l/O is HIGH when the nonvolatile write cycle is done.
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X84041
Figure 2. Write Sequence
CE
OE
WE
I/O (IN)
"0"
X
XXXXX
X A8
A7 A6 A5 A4 A3 A2 A1 A0
D7 D6 D5 D4 D3 D2 D1 D0
"1" "0"
I/O (OUT) RESET LOAD ADDRESS LOAD DATA
START NONVOLATILE WRITE
2704 ILL F04
Write Protection The following circuitry has been included to prevent inadvertent nonvolatile writes: -- The internal Write Enable latch is reset upon power-up. -- A reset sequence must be issued to set the internal write enable latch before starting a write sequence. -- A special "start nonvolatile write" command sequence is required to start a nonvolatile write cycle. -- The internal Write Enable latch is reset automatically at the end of a nonvolatile write cycle. -- The internal Write Enable latch is reset and remains reset as long as the WP pin is LOW, which blocks all nonvolatile write cycles.
SYMBOL TABLE
WAVEFORM
INPUTS Must be steady May change from LOW to HIGH May change from HIGH to LOW Don't Care: Changes Allowed N/A
OUTPUTS Will be steady Will change from LOW to HIGH Will change from HIGH to LOW Changing: State Not Known Center Line is High Impedance
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X84041
ABSOLUTE MAXIMUM RATINGS* Temperature under Bias .................. -65C to +135C Storage Temperature ....................... -65C to +150C Terminal Voltage with Respect to VSS ....................................... -1V to +7V DC Output Current ............................................... 5mA Lead Temperature (Soldering, 10 seconds) ...... 300C *COMMENT Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Supply Voltage X84041 X84041 - 3 X84041 - 2.7
Contact factory for availability.
RECOMMENDED OPERATING CONDITIONS Temperature Commercial Industrial Min. 0C -40C Max. +70C +85C
2704 PGM T02.2
Limits 5V 10% 3V 10% 2.7V to 5.5V
2704 PGM T03.2
D.C. OPERATING CHARACTERISTICS (VCC = 5V 10%) (Over the recommended operating conditions, unless otherwise specified.) Limits Symbol ICC1 ICC2 ISB ILI ILO VlL (1) VIH (1) VOL VOH Parameter VCC Supply Current (Read) VCC Supply Current (Write) VCC Standby Current Input Leakage Current Output Leakage Current Input LOW Voltage Input HIGH Voltage Output LOW Voltage Output HIGH Voltage Min. Max. 1 3 50 10 10 VCC x 0.3 VCC + 0.5 0.4 Units mA mA A A A V V V V Test Conditions OE = VIL, WE = VIH, I/O = Open, CE clocking @ 2MHz ICC During Nonvolatile Write Cycle All Inputs at CMOS Levels CE = VCC, Other Inputs = VCC or VSS VCC = 5V 10% VIN = VSS to VCC VOUT = VSS to VCC
-1 VCC x 0.7 VCC - 0.8
IOL = 2.1mA, VCC = 5V 10% IOH = -1mA, VCC = 5V 10%
2704 PGM T04.3
Notes: (1) VIL min. and VIH max. are for reference only and are not tested.
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X84041
D.C. OPERATING CHARACTERISTICS (VCC = 3V 10%) (Over the recommended operating conditions, unless otherwise specified.) Limits Symbol ICC1 ICC2 ISB1 ILI ILO VlL(1) VIH(1) VOL VOH Parameter VCC Supply Current (Read) VCC Supply Current (Write) VCC Standby Current Input Leakage Current Output Leakage Current Input LOW Voltage Input HIGH Voltage Output LOW Voltage Output HIGH Voltage Min. Max. 250 1 10 10 10 VCC x 0.3 VCC + 0.5 0.4 Units A mA A A A V V V V Test Conditions OE = VIL, WE = VIH, I/O = Open, CE clocking @ 2MHz ICC During Nonvolatile Write Cycle All Inputs at CMOS Levels CE = VCC, Other Inputs = VCC or VSS VCC = 3V 10% VIN = VSS to VCC VOUT = VSS to VCC
-1 VCC x 0.7 VCC - 0.4
IOL = 1mA, VCC = 3V 10% IOH = -400A, VCC = 3V 10%
2704 PGM T05.2
Notes: (1) VIL min. and VIH max. are for reference only and are not tested.
CAPACITANCE Symbol CI/O(2) CIN(2)
TA = +25C, f = 1MHz, VCC = 5V Parameter Input/Output Capacitance Input Capacitance Max. 8 6 Units pF pF Test Conditions VI/O = 0V VIN = 0V
2704 PGM T06.2
Notes: (2) Periodically sampled, but not 100% tested.
POWER-UP TIMING Symbol tPUR(3) tPUW(3) Parameter Power-up to Read Operation Power-up to Write Operation Max. 2 5 Units ms ms
2704 PGM T07
Notes: (3) Time delays required from the time the VCC is stable until the specific operation can be initiated. Periodically sampled, but not 100% tested.
A.C. CONDITIONS OF TEST Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels VCC x 0.1 to VCC x 0.9 5ns VCC x 0.5
2704 PGM T08.1
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X84041
EQUIVALENT A.C. LOAD CIRCUITS
5V 2.06K OUTPUT 3.03K 30pF
2.39K OUTPUT 4.58K 30pF 3V
2704 ILL F05.2
2704 ILL F05a.3
A.C. CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.) Read Cycle Limits - X84041 Symbol tRC tCE tOE tLOW tHIGH tLZ(4) tHZ(4) tOLZ(4) tOHZ(4) tOH tWES tWEH Parameter Read Cycle Time CE Access Time OE Access Time CE LOW Time CE HIGH Time CE LOW to Output In Low Z CE HIGH to Output In High Z OE LOW to Output In Low Z OE HIGH to Output In High Z Output Hold from CE or OE HIGH WE HIGH Setup Time WE HIGH Hold Time VCC = 5V 10% Min. Max. 300 45 45 70 70 0 0 30 0 0 30 0 25 25 VCC = 3V 10% Min. Max. 300 65 65 70 70 0 0 35 0 0 35 0 25 25 Units ns ns ns ns ns ns ns ns ns ns ns ns
2704 PGM T09.3
Notes: (4) Periodically sampled, but not 100% tested. tHZ and tOHZ are measured from the point where CE or OE goes HIGH (whichever occurs first) to the time when I/O is no longer being driven into a 5pF load.
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X84041
Read Cycle
tRC tLOW tCE tHIGH
CE
WE
tWES tOE
OE
tWEH tOHZ
I/O
tOLZ tLZ
DATA
tOH tHZ
HIGH Z
2704 ILL F06
Write Cycle Limits - X84041 Symbol tNVWC(5) tWC tWP tWPH tCS tCH tCP tCPH tOES tOEH tDS(6) tDH(6) tWPCS(7) tWPCH(7) tWPWS(7) tWPWH(7) Parameter Nonvolatile Write Cycle Time Write Cycle Time WE Pulse Width WE HIGH Recovery Time Write Setup Time Write Hold Time CE Pulse Width CE HIGH Recovery Time OE HIGH Setup Time OE HIGH Hold Time Data Setup Time Data Hold Time WP HIGH Before CE WP HIGH After CE WP HIGH Before WE WP HIGH After WE VCC = 5V 10% Min. Max. 10 300 30 200 0 0 30 200 50 50 30 5 500 500 500 500 VCC = 3V 10% Min. Max. 10 300 30 200 0 0 30 200 50 50 30 5 500 500 500 500 Units ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
2704 PGM T10.3
Notes: (5) tNVWC is the time from the falling edge of OE or CE (whichever occurs last) of the second read cycle in the "start nonvolatile write cycle" sequence until the self-timed, internal nonvolatile write cycle is completed. (6) Data is latched into the X84041 on the rising edge of CE or WE, whichever occurs first. (7) Periodically sampled, but not 100% tested.
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X84041
CE Controlled Write Cycle
tCPH tCP
CE
tOES tOEH
OE
tCS tCH tWP tWPH
WE
WP
tWPCS tDS
tWPCH tDH
I/O
DATA
tWC
HIGH Z
2704 ILL F07
WE Controlled Write Cycle
tCPH tCP
CE
tOES
OE
tCS
tCH tOEH tWP tWPH tWPWH
WE
WP
tWPWS tDS tDH
I/O
DATA
tWC
HIGH Z
2704 ILL F08
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X84041
PACKAGING INFORMATION
8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P
0.430 (10.92) 0.360 (9.14)
0.260 (6.60) 0.240 (6.10) PIN 1 INDEX PIN 1 0.300 (7.62) REF. 0.060 (1.52) 0.020 (0.51)
HALF SHOULDER WIDTH ON ALL END PINS OPTIONAL SEATING PLANE 0.150 (3.81) 0.125 (3.18)
0.145 (3.68) 0.128 (3.25)
0.025 (0.64) 0.015 (0.38) 0.065 (1.65) 0.045 (1.14) 0.020 (0.51) 0.016 (0.41)
0.110 (2.79) 0.090 (2.29)
0.015 (0.38) MAX.
0.325 (8.25) 0.300 (7.62)
TYP. 0.010 (0.25)
0 15
NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
3926 FHD F01
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X84041
PACKAGING INFORMATION
8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
0.150 (3.80) 0.158 (4.00) PIN 1 INDEX
0.228 (5.80) 0.244 (6.20)
PIN 1
0.014 (0.35) 0.019 (0.49) 0.188 (4.78) 0.197 (5.00)
(4X) 7
0.053 (1.35) 0.069 (1.75)
0.050 (1.27)
0.004 (0.19) 0.010 (0.25)
0.010 (0.25) X 45 0.020 (0.50)
0.050" TYPICAL
0 - 8 0.0075 (0.19) 0.010 (0.25) 0.016 (0.410) 0.037 (0.937) 0.250"
0.050" TYPICAL
FOOTPRINT
0.030" TYPICAL 8 PLACES
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F22.1
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X84041
PACKAGING INFORMATION
14-LEAD PLASTIC, TSSOP PACKAGE TYPE V
.025 (.65) BSC
.169 (4.3) .252 (6.4) BSC .177 (4.5)
.193 (4.9) .200 (5.1)
.047 (1.20)
.0075 (.19) .0118 (.30)
.002 (.05) .006 (.15)
.010 (.25) Gage Plane 0 - 8 .019 (.50) .029 (.75) Detail A (20X) Seating Plane
.031 (.80) .041 (1.05)
See Detail "A"
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F32
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X84041
ORDERING INFORMATION
X84041 Device
X
X
-X VCC Range Blank = 4.5V to 5.5V 3 = 2.7V to 3.3V 2.7 = 2.7V to 5.5V Temperature Range Blank = Commercial = 0C to +70C I = Industrial = -40C to +85C Package P = 8-Lead Plastic DIP S = 8-Lead SOIC V = 14-Lead TSSOP
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. Xicor's products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
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